Scaling of the gate dielectric is a challenge in improving performance of advanced field effect transistors. In a field effect transistor (FET) employing a silicon oxide based gate dielectric, the leakage current through the gate dielectric increases exponentially with the decrease in the thickness of the gate dielectric. Such devices typically become too leaky to provide high performance at or below the thickness of 1.1 nm for the silicon oxide gate dielectric.
High-k gate dielectric provides a technique to scale down the thickness of the gate dielectric without an excessive increase in the gate leakage current. However, high-k gate dielectric materials are prone to a change in the equivalent oxide thickness (EOT) because high-k gate dielectric materials react with oxygen that diffuses through the gate electrode or gate spacers. Regrowth of a silicon oxide interfacial layer between a silicon substrate and the high-k gate dielectric during high-temperature processing steps is a major obstacle to successful equivalent oxide thickness scaling. Particularly, typical stacks of a high-k gate dielectric and a metal gate are known to be susceptible to anneals at various temperatures in an oxygen ambient. Such anneals in an oxygen ambient result in regrowth of the silicon oxide interfacial layer and/or instability of the threshold voltage of field effect transistors.
In addition, the inversion oxide thickness Tinv and pFET threshold voltage (Vt) show a tradeoff relationship for a high-k/metal gate stack. Reference in this regard can be made to, for example, High-Performance High-k/Metal Gates for 45 nm CMOS and Beyond with Gate-First Processing M. Chudzik et al., VLSI symposium 2007, p. 194-195.